Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega...
by Dylan16807 on Monday March 09, 2020 @02:45AM
(#22523451)
> If you work with 100% cache misses, your mem will still be working at effective frequency of around 100 to 200Mhz
I think you mean 20MHz. Current DRAM is abysmal at random access.
Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega...
by baybal2 on Monday March 09, 2020 @04:44AM
(#22523917)
Yes, more so like this if you discard how it looks from the electrical side.
Even after bytes arrive to DRAM controller analog side, a lot of things have to happen before the data gets to the register. This accounts for the further five to tenfold increase in round trip latency
960MiB is prodigiously large for such a microscopic chip, but if it "only" gain 3-5 times latency reduction over external DRAM, it's still very far from a proper L3 implementation, and far behind L2.
Make DRAM work on 1Ghz+, and then you will see miracles. Imagine a fully synchronous on-die DRAM that can sit just behind L1, or even be connected to load registers directly.
The problem is that effective frequencies for memory round-trip haven't got up much since nineties. If you work with 100% cache misses, your mem will still be working at effective frequency of around 100 to 200Mhz