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A comment on IBM doubles its 14nm EDRAM density, adds hundreds of megabytes of cache. Parent comment

Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by mhh__ on Sunday March 08, 2020 @07:22PM (#22521406)
What do you mean by imperative? Static control by the program?
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Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by cryptonector on Monday March 09, 2020 @01:47AM (#22523255)
I'm guessing u/hinkley meant having an API for the cache, so a compiler could generate instructions to prefetch cache lines (and maybe even keep them hot) rather than depend on automatic (heuristic) cache management.
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Re:IBM doubles its 14nm EDRAM density, adds hundreds of mega... by Reelin on Monday March 09, 2020 @04:15AM (#22523806)
Just FYI, prefetch instructions are already a thing (at least on x86). At present they're only hints to the underlying heuristic system though. (https://www.felixcloutier.com/x86/prefetchh)

Cache-as-RAM is also a thing, and allows the sort of pinning you described. Pretty specialized use cases though. (https://stackoverflow.com/questions/41775371/what-use-is-the...)

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