Re:A Look at Celerity’s Second-Gen 496-Core RISC-V Mesh NoC
by AstralStorm on Monday January 13, 2020 @11:50AM
(#22036074)
Ask what's memory protection before it overwrites state used by another core. Then ask again how you synchronize these words from one with reads from another.
Yeah, it's not even eventual consistency. They get away with it by using a heavy mailbox message passing setup for synchronization and separate address spaces.
Yeah, it's not even eventual consistency. They get away with it by using a heavy mailbox message passing setup for synchronization and separate address spaces.