News for hackers. Stuff that matters.
Re:Reviewing Bad Schematics as EE Interview Tactic by madengr on Monday December 23, 2019 @05:50PM (#21868193)
Here are some of my RF specific interview questions. Spend no more than 1 minute on each.

Power Amplifiers

Q: Where do GaAs/GaN FETs DC gate currents originate, and why are they positive and negative?

Q: How would you temperature compensate the transistor DC bias.

Q: What is AM-AM and AM-PM distortion and how would you measure it?

Q: Give an example of a “memory effect”.

Passive RF/Microwave Circuits

Q: How would you measure unloaded Q of a resonator?

Q: What is self-resonant frequency of a component (i.e. chip L or C) and when is it useful.

Q: Why does a stripline coupler typically perform better than microstrip?

Q: What’s the characteristic impedance and electrical length for the lines in a 2-way Wilkinson splitter.

Q: Where does the current flow on a microstrip line and its return path?

Test and Measurement

Q: What’s the difference between RBW and VBW on a spectrum analyzer?

Q: When is a sliding load used in VNA calibration and how does it work?

Q: What does noise marker mode do on a spectrum analyzer?

Q: How would you measure a SMT part at several GHz with proper reference planes?

Q: What’s a quick way to tell if your spectrum analyzer is contributing to IMD3.

Digital Comms

Q: Why are RRC filters used so frequently?

Q: Describe the flow of PSK receiver?

Q: What is an Error Vector Magnitude (EVM) measurement?

Q: What effect does clock jitter have on an ADC or DAC.

Q: Would a class C amplifier work better with OFDM or FSK?

Antennas

Q: What typically limits the bandwidth on a single frequency patch antenna?

Q: What’s common mode radiation on a coax (to antenna) transition and what are a couple of ways to minimize it.

Q: What happens to an antenna’s input impedance and directivity when you move it very close to a “ground plane”.

Q: What’s an IFA or PIFA antenna and how does it relate to a monopole; why are they so common in compact devices.

Q: Given a VNA and two linearly polarized horn antennas with known gain, how would you measure the gain of a circularly polarized antenna?

RF Front Ends

Q: What are the typical blocks in a superhet receiver (or down conversion chain)?

Q: What typically determines diode mixer linearity?

Q: What’s IMD?

Q: What’s more important in LNA; noise or impedance match?

Q: What’s cross-modulation?

Synths and Oscillators

Q: What are the advantages and dis-advantages of a Frac-N over an Integer-N synth?

Q: What specs would you look for in a linear regulator to isolate a synth analog section from a switching supply?

Q: Given you don’t care about settling time, how would you set loop filter bandwidth to achieve best noise performance?

Q: Given you don’t care about settling time, how would you set loop filter bandwidth to achieve best noise performance?

Q: What do synth ICs have charge pump trim settings (i.e. upper and lower different gains)?

Connectors and Waveguides

Q: What is skin effect?

Q: What is the torque specification for a 3.5mm connector?

Q: Why is nickel used in plating processes? What effect does it have on RF?

Q: What’s the highest frequency that an SMA connector can be used for TEM propagation? What happens above that?

Q: If you needed to slice a rectangular waveguide in half, would you slice down the broad wall or the narrow wall? Why?

Simulation

Q: Why would use you use 2D thick metal (or 3D EM) on edge coupled lines? Is there a rule of thumb?

Q: Would you use harmonic balance or transient simulation (or both) to model a simple diode detector?

Q: What are some quick methods to determine if your EM simulation is plausible?

Q: Given microstrip element models, would you model a short, wide line as a line with two steps, or a cross with two long stubs; the layout is identical.

Q: What type of EM simulator (2D or 3D, infinite or finite boundary, gridded or gridless, time or frequency domain) would you use for: patch antenna, planar filter, horn antenna, cavity filter. Why?

Re:Reviewing Bad Schematics as EE Interview Tactic by imba404 on Monday December 23, 2019 @10:26PM (#21869607)
Dude, I work in RF and it would take me more than a minute to remember some of the answers to these questions.
Re:Reviewing Bad Schematics as EE Interview Tactic by kragen on Tuesday December 24, 2019 @03:00AM (#21870613)
These are for the most part considerably harder than noticing a backwards protection diode or a missing base resistor.
Re:Reviewing Bad Schematics as EE Interview Tactic by nullc on Tuesday December 24, 2019 @04:39AM (#21870926)
Some are hard, other like asking about a Class C amplifier with OFDM are just lol.
Re:Reviewing Bad Schematics as EE Interview Tactic by kragen on Tuesday December 24, 2019 @07:36AM (#21871599)
That was one of the few I could do! I figured FSK would survive Class C distortion.