Re:Three of Apple and Google’s former star chip designers la...
by jabl on Saturday November 23, 2019 @06:18PM
(#21617286)
I don't think it's as easy as saying that Aarch64 dropped thumb, therefore compressed instructions are dumb.
- Like somebody already pointed out, thumb is a different mode, whereas RISC-V C (RVC) can be freely mixed with normal 32-bit instructions.
- And speaking of higher end processors, x86 does very well in that space despite requiring much more complex decode than RVC.
- Aarch64 has more complex addressing modes (base + index<<shift in particular) whereas RISC-V needs both RVC and fusion to do the same with similar code size and execution slot occupation. Personally, I'm leaving towards thinking that it was a mistake for RISC-V to not support such addressing modes. Unless you're aiming for something really super-constrained in terms of gate counts, having an adder and small shifter as part of your memory pipeline(s) seem like an obvious choice. And thus, having single instructions to use those pipelines isn't really committing any sins against the RISC philosophy.
- Like somebody already pointed out, thumb is a different mode, whereas RISC-V C (RVC) can be freely mixed with normal 32-bit instructions.
- And speaking of higher end processors, x86 does very well in that space despite requiring much more complex decode than RVC.
- Aarch64 has more complex addressing modes (base + index<<shift in particular) whereas RISC-V needs both RVC and fusion to do the same with similar code size and execution slot occupation. Personally, I'm leaving towards thinking that it was a mistake for RISC-V to not support such addressing modes. Unless you're aiming for something really super-constrained in terms of gate counts, having an adder and small shifter as part of your memory pipeline(s) seem like an obvious choice. And thus, having single instructions to use those pipelines isn't really committing any sins against the RISC philosophy.