FYI the comparison is to the A72, not A73.

A72 is a mobile chip, so still not particularly relevant to tuna-fish's claim about high end servers. The raspberry pi 4 is not a high end server.

> half the die area

Much of this is free when comparing a 16nm design to a 7nm design. See footnote 1 in your link.

EDIT: I was curious, so I looked up the transistor density of tsmc 16nm vs 7nm.

16nm: 28.8 MTr/mm^2

7nm: 96.5 MTr/mm^2

So I think that sifive core with "half the area" is actually not quite as good as a die shrink of the A72.

Necro-reply here, but yes you got me. 2.63mm2 on 7nm is about 8mm2 on 16nm, which is same as the A72. And it was the A72, the A73's predecessor. I think the point stands that RISC-V is suited for high-performance designs, which was the original contention. If a startup can do 3-way OoO, an org with more resources can do 7-way OoO along with more sophisticated branch prediction and stronger cache coherency to catch up to state-of-the-art cores. There isn't anything in the RISC-V ISA preventing that.

>> A72 is a mobile chip

So is Apple A13. And yet it's been reported to outperform all Intel desktop CPUs in single core performance (I find the benchmark dubious, but I do believe it's close, and faster than it has any right to be given the super low power consumption). The only reason it doesn't do so in multicore perf is the limited TDP - a concern which does not exist in high end chips.

https://news.ycombinator.com/item?id=21033371

Sure. Even all of Apple's macOS-Server machines running the Apple Cloud are powered by A13 chips these days. /s

Non sequitur.