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Re:SiFive Announces First RISC-V OoO CPU Core by cfallin on Wednesday October 30, 2019 @11:35AM (#21398876)
"IP core" can mean "soft IP", which is just RTL, or "hard IP", which is a full layout (set of mask layers), ready to put on silicon. I haven't read the SiFive announcement closely, but if they're quoting area/frequency/power numbers, it would most likely be the latter.
Re:SiFive Announces First RISC-V OoO CPU Core by gnode on Wednesday October 30, 2019 @11:53AM (#21399065)
Interestingly, although all the RTL for the SiFive Freedom platform is in the SiFive's GitHub repository, and they've produced chips and boards (with public schematics and BOM), the hard IP doesn't appear to be public.

I wonder if this is because the hard IP is specific to the fabs' trade secret tooling, and so subject to their NDAs, making it impossible to distribute publicly.

Re:SiFive Announces First RISC-V OoO CPU Core by monocasa on Wednesday October 30, 2019 @12:06PM (#21399201)
You're on point with the second paragraph. I only know of one chip fab that has it's design rules public, and they're an open source fab running out of HKUST that'll give you about Arduino level gate counts.
Re:SiFive Announces First RISC-V OoO CPU Core by wolf550e on Wednesday October 30, 2019 @12:52PM (#21399798)
Why can't a fab with something like 28nm use public design rules? I guess there aren't valuable trade secrets still in a process that old. But some chips can usably be made on such a process.
Re:SiFive Announces First RISC-V OoO CPU Core by Sanzig on Wednesday October 30, 2019 @01:00PM (#21399894)
There's a lot of mixed-signal specialty ASICs at the 350 nm and 180 nm nodes. As long as you don't need the density, it's a great option. Masks are relatively cheap and the processes are dialed in extremely well at this point. Just because the tech is 20-30 years old doesn't mean it's not useful.
Re:SiFive Announces First RISC-V OoO CPU Core by monocasa on Wednesday October 30, 2019 @02:22PM (#21400831)
There's absolutely valuable trade secrets even at 28nm. For starters, a fab's work at 28nm would absolutely inform descions on newer nodes. Additionally, the older nodes don't just shut down their lines, but are dependent on continued use to pay off their massive capital investment. They're still competing with the other 28nm fabs.
Re:SiFive Announces First RISC-V OoO CPU Core by namibj on Thursday October 31, 2019 @03:15PM (#21412521)
I wish one of them would just try and release a 180nm process in a way that allows public domain maskset distribution.

If it flops, so be it; if not, many people like myself can suddenly start hacking on analog or mixed IC designs for potentially exotic things, like analog-computer-based UAV controllers that integrate the control loop with e.g. external feedback like simple doppler/chirp radar to reach microseconds of feedback latency and thus enabling monolithic closed-loop control.

A miniaturized version of https://www.research-drone.com/en/ with the blade's counterweight being a single neodymium magnet in an outrunner configuration and a ferrite stator fabricated using SMD inductor technology to target the 5g (+ payload + battery) UAV class would be interesting, but the ~3KHz (typical disc loading and high subsonic tip speed) rotation rate (~200k rpm) make software control of the motor driver difficult.