That is wrong generally. Not sure how you got that idea either. The chips that overclock the highest are typically the most efficient ones, too. A 9900K that can run at 5.3 GHz at 1.35v is going to use less power than a 9900K that needs 1.5v to run at 5.3 GHz. At any frequency. Because the "golden" chip simply leaks less power, and needs less voltage at any given frequency. Lower TDP parts aren't special in any way, they just have lower clocks. If you limit the clocks on higher TDP parts, you get the same (or better) power consumption.
To drive the transistors in a chip you need to supply or sink enough charge so that the MOSFET will change state. The rate at which we can supply this charge places a fundamental limit on the switching speed of this transistor. Because until we overcome this charge requirement the transistor will not turn on/off.
Now the speed we can move this charge in and out of the input of the chip is governed by resistance. Higher resistance between VCC and the gate means it takes longer to over come the capacitance and change the state of the MOSFET.
Lets say for some given arbitrary Transistor its input capacitance is some 50pF , and lets also say our resistance to vcc is 10 ohm, then tao or the time constant is nothing but RC or 500 pico-seconds. In other words the maximum switching speed that we can see on the output is 1/tao or some 2Ghz. Now logic circuits are more than one transistor deep, and we can't reasonably run the circuit at exactly tao (Also at t=tao the gate is not exactly vcc it is ~.63vcc as this is an exponential function) and expect any level of signal integrity. But this tao is sort of a hard limit to switching speed as it is the time it takes the transistor to swap state.
In some sense low resistance is a boon. Low resistance means low tao, as tao is just RC. If tao is small than the transistor changes state more quickly. As a result for a given clock, the transistor has longer to overcome any inductance/capacitance present and is able to emit a cleaner signal.
But what lower resistance means is that you have higher power consumption as: p=iv & v=ir -> P=V^2/R So we see low resistance-> higher current. and higher current -> more power.
So we see it is a balancing act. We can have higher speeds or we can have lower power but not both. So if we are binning for a certain speed we are also binning for a certain power consumption characteristic. By selecting chips with speeds greater than XGhz we are also selecting chips with internal resistance < R.
Now what you said about over clocking is true. But because of an added twist.
Say we are binning a set of R that satisfy clk > XGhz. So naturally some subset of R will still be comfortably capable of XGhz while using less power than the average member of R. Now the chip has real limits to its capability to perform while hot. So this subset performs well as it is just low enough resistance to run a XGhz while limiting power use. On the high edge of the set R, we see chips that barely made XGhz and cant clock better. On the low edge of set R we see chips that are runing so hot as to barely maintain XGhz. So there is a sweet spot.
I think you're forgetting time in this equation. If two otherwise identical MOSFETs have different gate resistances, the lower-resistance MOSFET will charge faster and draw switching current for less time.
Take this all the way back to a simple linear circuit: a 1-ohm, 1-farad RC circuit will have a time constant of 1s, and if supplied with 1V the current will be I(t) = exp(-t). The power lost to heat in the resistor is then I^2R = exp(-2t), and integrated from 0 to infinity the net energy loss is 0.5J.
If instead the circuit has a resistance of 0.5 ohm, the resulting current is I(t) = 2exp(-2t). Power loss is I^2R = (0.5)*(4 exp(-4t)) = 2 exp(-4t), and integrated from 0 to infinity gives a net energy loss of again 0.5J.
In the meantime, the lower-resistance MOSFET is likely to save power from other effects. Most notably, faster switching implies the transistor spends less time in its linear region where it itself acts as a resistor between source and drain.
1 Ohm Case : P_res = integral exp(-2t) from 0 to tao -> .4323J 1/2 Ohm Case : P_res = integral 2*exp(-4t) from 0 to tao -> .4908J
Of course the effect diminishes greatly (to zero as you showed) as the switching time increases. But we are dealing with a great number of transistors switching very many times so the effect is still noticeable given timings are tight enough.
The thought on power savings as you mention is interesting but i am unsure off the top of my head of it.
If a transistor is only reciving 5v than it is fair to say the power consumed is equal.
But realisticly the input could change every clock cycle and we would see the cases vary.
The reason I only integrate to tao was to show if the input switches before t=infinity then a diffrence between cases clearly manifest. But as you say, when it does not switch for time t>>tao the diffrence is small.
So as you said, its "just a slightly worse binned version" but worse in terms of max clock not performance/watt.
Although there isnt a 'hard' definition of TDP AMD has typically rated there chips more accurately[ii] than intel in the past [0], but that said AMD's TDP is still lower than absolute max power draw.
[i]- Memories from working in validation, although this was not focus of my work, this is what I recall on the topic.
[ii]- from amd's data sheet "The maximum power a processor draws for a thermally significant period while running commercially useful software. The constraining conditions for TDP are specified in the notes in the thermal and power tables."
NOTE! This source is old!! [0]-https://www.anandtech.com/show/2807/2