Re:RISC-V formal spec public review
by edflsafoiewq on Friday June 21, 2019 @02:01AM
(#20240220)
On x86 you'd do a bigint add with an ADC chain. In RISC-V I think it would be a lot more branchy.
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I know nothing about RISC-V, but my usual way of finding out how to do something standard with a given instruction set is to ask a compiler. There are online compilers, such as this one: https://cx.rv8.io/ Just type in "__int128 add(__int128 a, __int128 b) { return a + b; }" on the left, stick "-O2" into the "Compiler options", and see what you get! I don't know whether that particular compiler is doing the right thing, of course, but it gives you an idea and it's definitely less work than reading the spec.
Re:RISC-V formal spec public review
by waterhouse on Friday June 21, 2019 @04:22AM
(#20240842)
No need for branches, see comment above demonstrating sltu.
For a long carry chain, I guess it might look like this:
; Inputs: x = 4-word number, in a3:a2:a1:a0,
; y = 1-word number, in a4.
; Output: x+y, 5-word number, in a4:a3:a2:a1:a0.
add a0, a0, a4
sltu a4, a0, a4 ; a4 = carry bit
add a1, a1, a4
sltu a4, a1, a4 ; a4 = carry bit again
add a2, a2, a4
sltu a4, a2, a4
add a3, a3, a4
sltu a4, a3, a4
Re:RISC-V formal spec public review
by edflsafoiewq on Friday June 21, 2019 @04:56AM
(#20240948)
Ah, nice, thank you! I must have missed sltu.