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A comment on MIPS R3000. Parent comment

Re:MIPS R3000 by pkaye on Thursday June 20, 2019 @02:30PM (#20235783)
Alpha had a weakly-ordered memory model though.
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Re:MIPS R3000 by monocasa on Thursday June 20, 2019 @02:57PM (#20236081)
Yeah, but it wasn't that big of a deal in practice. I sort of like that it was such a weak memory model that you just explicitly had to synchronize any sorts of cross thread comms.
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Re:MIPS R3000 by ncmncm on Thursday June 20, 2019 @09:45PM (#20239170)
MIPS never had any memory model at all! They might have one, by now, most likely cribbed from PPC, ARM, or Itanic. Or maybe more than one!
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