Re:Cray, AMD to Extend DOE’s Exascale Frontier
by Symmetry on Tuesday May 07, 2019 @09:27AM
(#19849102)
PCIe provides communication but isn't intended to provide memory coherency. There's a lot of work that goes on in figuring out which cache(s) have a copy of which cache line and figuring out how to resolve conflicting access needs.
Re:Cray, AMD to Extend DOE’s Exascale Frontier
by gnode on Tuesday May 07, 2019 @09:30AM
(#19849115)
Infinity Fabric / HyperTransport is generally lower level and lower latency than PCIe. It's aimed more for use as a front-side bus than a peripheral interconnect. A better analogue would be Intel's QuickPath Interconnect.
What interconnects do these sorts of machines use? I assume even 100GbE isn't enough?
Just curious. It's interesting what exists in the "so far beyond my price range as to be ludicrous" category.