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Re:Belgian programmer solves MIT’s 20-year-old time capsule ... by justindrake on Tuesday April 30, 2019 @04:41AM (#19786123)
Ballpark latency numbers per 2048-bit modular multiplication:

CPU—1100ns

FPGA—66ns

ASIC—1ns (expected)

If you're a hardware engineer (or mathematician) interested is building an ultra-low latency ASIC, please email [email protected]

Source: https://twitter.com/drakefjustin/status/1123143447551053824

Context: https://www.youtube.com/watch?v=zqL_cMlPjOI

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