Verilog sources for Western Digital's open source RISC-V core

Re:Verilog sources for Western Digital's open source RISC-V ... by jhallenworld on Sunday January 27, 2019 @12:14PM (#19012602)

I like the small number case: they use a very old logic minimization program to generate the equations for it:

Otherwise it's taking 32 cycles to do the division. There is a count for this.

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