Verilog sources for Western Digital's open source RISC-V core

Re:Verilog sources for Western Digital's open source RISC-V ... by xvilka on Sunday January 27, 2019 @08:12AM (#19011558)

Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3].

[1] https://github.com/freechipsproject/FIRRTL

[2] https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...

[3] https://github.com/SymbiFlow/ideas/issues/19

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Re:Verilog sources for Western Digital's open source RISC-V ... by NotCamelCase on Sunday January 27, 2019 @08:53AM (#19011665)

It's a neat idea, but to me, that's like it. For SW, LLVM serves two-way: 1)target any (supported) arch you like with your language of choice, 2)customize your toolchain to generate native machine code (i.e. GPU shader langauges) from any (supported) language.

I'd say putting yet another middleman between your logic compiler/netlist and what you actually use is not the best course of action for HW implementations. Even HLS has a big friction for use and is hardly picked up, with its obvious, immediate advantages.

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Re:Verilog sources for Western Digital's open source RISC-V ... by diarmuidc on Sunday January 27, 2019 @08:39AM (#19011628)

A HDL that no one in the industry uses?

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