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A comment on Verilog sources for Western Digital's open source RISC-V core. Parent comment

Re:Verilog sources for Western Digital's open source RISC-V ... by zokier on Sunday January 27, 2019 @04:20AM (#19011035)
> It looks like it's a Harvard-architecture core. That means separate buses for data and instructions, which is not common outside of embedded or specialized systems.

I'd point out that WASM is also Harvard architecture so that's not so exotic anymore

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