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A comment on Verilog sources for Western Digital's open source RISC-V core. Parent comment

Re:Verilog sources for Western Digital's open source RISC-V ... by m0zg on Saturday January 26, 2019 @10:55PM (#19010269)
That sounds like considerably more work than I was hoping it would be. So the follow-up question, then. Who is this release for, in your opinion?
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Re:Verilog sources for Western Digital's open source RISC-V ... by FPGAhacker on Saturday January 26, 2019 @11:00PM (#19010278)
I don't know why WD released this, but it would be useful for people building SoC ASICs that don't want to license an ARM core. Depending on the licensing.
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Re:Verilog sources for Western Digital's open source RISC-V ... by antpls on Sunday January 27, 2019 @03:07AM (#19010849)
Maybe this will be picked as teaching material in universities by students or teachers, which means potential future candidates for WD.

Maybe it's a way to help existing experts to federate around real use cases to discuss further field improvements, which means outsourced R&D for WD.

Eventually, it will be less work in the future once more people get interested in the subject.

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