That IP block is only used to talk to the PHY, in this case the high-speed transceiver hardware built into the 7-series FPGAs. You still have to license some (very) non-free IP from a vendor like Northwest Logic or Xillybus if you don't want to take on a major R&D project to get PCIe up and running.

Then there's the question of driver licensing on the OS side, if you want Windows support. Not sure if there are any prepackaged free-as-in-beer solutions for that. There were none when I looked into it a few years ago.

UCSD's RIFFA [1][2] open-source PCIe framework includes Windows 7 & Linux drivers and their 2015 paper [3] claims support for Xilinx 7-series FPGAs.

[1] https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-...

[2] https://github.com/KastnerRG/riffa

> RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. The framework requires a PCIe enabled workstation and a FPGA on a board with a PCIe connector. RIFFA supports Windows and Linux, Altera and Xilinx, with bindings for C/C++, Python, MATLAB and Java .. Users can communicate with FPGA IP cores by writing only a few lines of code ... No knowledge of bus addresses, buffer sizes, or PCIe packet formats is required. Simply send data on a FIFO interface and receive data on a FIFO interface. RIFFA does not rely on a PCIe Bridge and therefore is not subject to the limitations of a bridge implementation. Instead, RIFFA works directly with the PCIe Endpoint and can run fast enough to saturate the PCIe link.

[3] https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.u...

Hmm, that looks really cool, thanks. It definitely wasn't around when I needed it, and I'm surprised not to have heard of it in the meantime. Seems like a legitimate end-to-end solution.