A similar device, https://picoevb.com, has a virtual JTAG cable.
[1] http://xilinx.eetrend.com/files-eetrend-xilinx/download/2013...
Then there's the question of driver licensing on the OS side, if you want Windows support. Not sure if there are any prepackaged free-as-in-beer solutions for that. There were none when I looked into it a few years ago.
[1] https://forums.xilinx.com/t5/Xcell-Daily-Blog-Archived/Need-...
[2] https://github.com/KastnerRG/riffa
> RIFFA (Reusable Integration Framework for FPGA Accelerators) is a simple framework for communicating data from a host CPU to a FPGA via a PCI Express bus. The framework requires a PCIe enabled workstation and a FPGA on a board with a PCIe connector. RIFFA supports Windows and Linux, Altera and Xilinx, with bindings for C/C++, Python, MATLAB and Java .. Users can communicate with FPGA IP cores by writing only a few lines of code ... No knowledge of bus addresses, buffer sizes, or PCIe packet formats is required. Simply send data on a FIFO interface and receive data on a FIFO interface. RIFFA does not rely on a PCIe Bridge and therefore is not subject to the limitations of a bridge implementation. Instead, RIFFA works directly with the PCIe Endpoint and can run fast enough to saturate the PCIe link.
[3] https://87c7e184-a-d06fb7e1-s-sites.googlegroups.com/a/eng.u...
Also, the mandatory heatsink for "heavy designs" (without any notion of what that means) is a bit...limiting.
[1] https://github.com/enjoy-digital/litepcie