Re:Intel Unfolds Roadmaps for Future CPUs and GPUs
by walterbell on Monday December 17, 2018 @11:10AM
(#18699805)
> We figure that Intel is hedging a bit these days, and aims to convert the monolithic Cores and Xeons into multichip module designs, mixing chiplets with different functions in appropriate processes, as AMD, Xilinx, and Barefoot Networks have confirmed they are doing with their chips coming in 2019. We will not be surprised at all if processing cores of the future “Ice Lake” Xeons are implemented in 10 nanometers but other parts of the socket – probably memory and I/O controllers – stay in a very refined and mature 14 nanometer process.
So this would improve performance/watt for compute but not I/O?
Re:Intel Unfolds Roadmaps for Future CPUs and GPUs
by rbanffy on Monday December 17, 2018 @11:36AM
(#18699979)
Yes, but if the overall power consumption of the 14 nm part is not a significant fraction of the total package consumption, it doesn't make much sense to move it to the newer process. Also, the 14 nm factories are already churning out parts at a very predictable yield.
Re:Intel Unfolds Roadmaps for Future CPUs and GPUs
by PedroBatista on Monday December 17, 2018 @01:10PM
(#18700726)
Disregarding the fanboyism, we all must thank AMD for the advances and much better deals we are getting these days.
2 years ago, Intel was laughing at "glued-together" CPUs, rolling their eyes at anything with more than 4 cores and more recently implying that CPUs with different process sizes was "cheating".
Re:Intel Unfolds Roadmaps for Future CPUs and GPUs
by blackstrips on Monday December 17, 2018 @09:26PM
(#18704083)
> more recently implying that CPUs with different process sizes was "cheating".
Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost.
There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection.
I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache.
As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.
So this would improve performance/watt for compute but not I/O?
2 years ago, Intel was laughing at "glued-together" CPUs, rolling their eyes at anything with more than 4 cores and more recently implying that CPUs with different process sizes was "cheating".
Look at them now..
Not sure where you heard that because Intel’s CPUs have different feature sizes among the layers. It’s done to cut cost.
There is a downside to “glued-together” CPUs as Zen has demonstrated - their L3 cache is splitted and connected by a relatively slow connection.
I hope Intel continues to make “non-split” CPUs where all cores have equal access to single huge L3 cache.
As for moving components off die ... IIRC the Pentium Pro has its L2 cache on a different die but in the same package and the Pentium 2 went even further with the L2 cache on a daughterboard. This isn’t new to anyone.
It was quite remarkable.
http://semimd.com/blog/2014/09/02/intel-announces-new-interc... https://www.intel.com/content/www/us/en/foundry/emib.html https://www.extremetech.com/computing/254728-intel-discusses... https://www.storagereview.com/intel_unveils_its_stratix_10_m...
Edit: typo