Re:Bfloat16 – Hardware Numerics Definition [pdf]
by staticfloat on Saturday November 17, 2018 @10:06AM
(#18475788)
Google uses it on their TPUs [0]. If you're interested in how it would effect the numerical stability of an algorithm you want to use, there is a Julia package that makes prototyping linear algebra over this datatype pretty straightforward [1].
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by scottlegrand2 on Saturday November 17, 2018 @11:30AM
(#18476127)
And Facebook is taking this even further. And while all these things are very cool, do not let ASIC designers claim they are barriers to entry for GPUs and CPUs. Whatever variants of this precision potpourri catch on are but a generation away from incarnation in general processors IMO...
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by marcyb5st on Saturday November 17, 2018 @10:03AM
(#18475776)
Google's TPUs use them. But it has been for a year. I don't agree with the "new" or "Intel's" in the title.
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by masklinn on Saturday November 17, 2018 @10:36AM
(#18475895)
And TPU uses them because Tensorflow uses them, it's been present since the first public commit: https://github.com/tensorflow/tensorflow/blob/f41959ccb2d9d4...
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by twtw on Saturday November 17, 2018 @01:59PM
(#18476837)
I would be extremely surprised if the motivation for putting bfloat16 in tensorflow was not the TPU. That first public commit was ~1.5 years before TPUv2 was announced at I/O, so it was almost certainly already in development.
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by vrv on Saturday November 17, 2018 @03:02PM
(#18477087)
bfloat16 was first in DistBelief, so it actually predates TensorFlow and TPUs (I worked on both systems). IIRC the motivation was more about minimizing parameter exchange bandwidth for large-scale CPU clusters rather than minimizing memory bandwidth within accelerators, but the idea generalized.
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by marcyb5st on Saturday November 17, 2018 @11:04AM
(#18476019)
Thank you! I didn't know this. I thought they introduced them shortly after announcing TPU v1 in the 2016 (or 2017, can't remember) Google I/O.
Re:Bfloat16 – Hardware Numerics Definition [pdf]
by shaklee3 on Saturday November 17, 2018 @06:45PM
(#18478017)
Why is it clever to change the mantissa and exponent size? I thought the clever ones were the nervana flexpoint which seemed at least partially novel. And it's interesting Intel isn't pushing that format given nervana's asic had it.
Is anyone else using it?