Google produces their own sticks anyway.

At one point they were taking chips that had failed manufacturers QA, sticking them on DIMMs themselves in a way so that the ECC would cover those errors, and just running jobs on many machines to make up for the reduced ability of ECC to make guarantees.

And the make their own motherboards too, so just soldering down LPDDR isn't out of the question.

Wow, this sounds really interesting.

Do you have a link where I can read more about this?

It's nearly impossible to find. Google's paper put out by an intern right after that DRAM errors are way bigger than expected (yeah no shit if they're pulling this crap) dominates the results.

For a while I thought I was going crazy, but a comment from someone on this article implies he saw the same slide deck. https://arstechnica.com/information-technology/2009/10/dram-... I haven't been able to get anyone to reconfirm it from Google's end, my sense is that it's information that wasn't supposed to be released.

LPDDR doesn't come in modular form. It's always soldered onto the same PCB as the processor. The number of packages used is determined by the data bus width of the processor. If Google has access to a processor with a DRAM controller that supports LPDDR4 and ECC, they can design a suitable motherboard.

That is typical usage but it isn't the required usage. It is straight forward to generate a controller ASIC that would provide the appropriate bus signals and drive levels for these to operate on a module.

The signal integrity at 0.6V at whatever frequency these are at, across a connector must be horrible. Are people doing this?

I have seen LPDDR modules where the ASIC provides the connector signals. So they run 0.6V between the LPDDR chips and the ASIC, then the ASIC runs 1.8V on the connector.

I don't think I follow your topology. The asic is driving 1.8V to a dimm with 3 LPDDR chips on it? At ddr4 speeds?

The modules in question were for an embedded system with 3 different memory size options. The LPDDR chips and ASIC were on the memory module (4, 6, or 8 LPDDRs), and the module connected to the baseboard with a high speed mezzanine connector.

Is this something you are looking to build for your own system? I assume the ASIC was proprietary but I could reach out to the vendor and see where they had the modules made (or if they were built in house).

Right I see. So memories and controller on the same module just like normal. My original comment was concerning parallel 0.6V signalling at ddr4 speeds over a connector - which isn't happening here. Or probably anywhere.