The signal integrity at 0.6V at whatever frequency these are at, across a connector must be horrible. Are people doing this?

I have seen LPDDR modules where the ASIC provides the connector signals. So they run 0.6V between the LPDDR chips and the ASIC, then the ASIC runs 1.8V on the connector.

I don't think I follow your topology. The asic is driving 1.8V to a dimm with 3 LPDDR chips on it? At ddr4 speeds?

The modules in question were for an embedded system with 3 different memory size options. The LPDDR chips and ASIC were on the memory module (4, 6, or 8 LPDDRs), and the module connected to the baseboard with a high speed mezzanine connector.

Is this something you are looking to build for your own system? I assume the ASIC was proprietary but I could reach out to the vendor and see where they had the modules made (or if they were built in house).

Right I see. So memories and controller on the same module just like normal. My original comment was concerning parallel 0.6V signalling at ddr4 speeds over a connector - which isn't happening here. Or probably anywhere.