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A comment on The Fiasco microkernel. Parent comment

Re:The Fiasco microkernel by klez on Thursday October 11, 2018 @08:26AM (#18192889)
Ehm, no, it has nothing to do with the cache, it's just a successor of L3[0].

[0] https://en.wikipedia.org/wiki/L4_microkernel_family#L3

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Re:The Fiasco microkernel by indigochill on Thursday October 11, 2018 @08:31AM (#18192923)
Ah, thanks. Hadn't heard of it, but now I know!
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