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Re:The iPhone XS and XS Max Review: Unveiling the Silicon Se... by tinus_hn on Saturday October 06, 2018 @04:17AM (#18154143)
Due to all that legacy the instruction decoder has a lot less opportunity for optimizations.

There may be a physical limit to the size of transistors but the limit of computing performance is not ‘what Intel is doing’. There’s more to performance than instructions per second or clock frequencies. In fact these don’t lead to the same performance at all as ARM is RISC and x64 is CISC.

Re:The iPhone XS and XS Max Review: Unveiling the Silicon Se... by z0d on Saturday October 06, 2018 @11:50AM (#18155724)
That RISC and CISC, nobody mentioned until yours. Why are people only caring about Perf/watt or the SoC beating out the ST perf of the Skylake uarch. RISC based processor with that level of cache is always having an advantage due to the Load and Store at register level (esp in this A12 case of having HUGE L$) vs the CISC's more transistor level perf + DRAM to exec instructions, causing higher TDP requirements PLUS the multi instruction execution parallelism capabilities. And entirely different code of AArch64 and x86_64.

Add the GPU and Direct X, and Encode/Decode functionality I know this is not the subject, the ARM processors simply cannot keep up. The author did also mention the limitations of the comparison also as mentioned above the Skylake Xeon is capable of running Hex channel ECC Memory with huge capacity that alone will outpace everything on ARM it's not a fair share of comparison at all. GB is an OS level optimized bench. There's simply no comparison point that exists.

Like I'd say to the author do a 4D render bench like Cinebench then we talk on this. He should at-least have mentioned the uarch part. Also on a side note, Apple underselling the chips ? That's really first, since Apple always over promises. Their latest meltdown on the MacBooks with low quality/specced VRM throttling the CFL machines is a joke.