Did you consider using modern e.g. DLP chips or so for a maskless fab? It would not work on too modern nodes anyway, just due to the restriction to ~405 nm by the aluminium reflectors on the chip turning i-Line and deeper into more and more heat you can't get away from the chip. 180 nm seems to be what one could hope for with an immersion stepper at 405 nm without too much trickery, but the next one up should be possible with dry exposure. Hit me up if you want help or so with a maskless, sane-priced-chips yielding fab. There are just so many applications once you have the same price per chip at 1 or 5 or 100. Things like custom hardwired monolithic analogue compute could enable e.g. micro drones and likely lots of other stuff if it's cheaper to use some tool to generate the analogue or mixed circuit that will replace all logic parts on some circuit board, leaving only power handling components and those that don't work inside an IC. Maybe the freedom to create a monolithic version of an HB100 radar module, allowing a heterodyne design due to the savings from integration, with the needed experimentation being possible just because iterations are neither expensive nor long (comparable to Chinese PCB manufacture, so something under a week).

This is a good thought. The short answer is of course no, I didn't because I was looking at preserving an existing line rather than build a new one. However I think there is a lot of merit in penciling out a closed cell[1] (mostly) dry line. The cost to develop the equipment would be pretty high though, perhaps prohibitive relative to the ability to resell that gear.

[1] Where wafers are always in a closed container, no clean room required.

Oh, I very much meant using the chemical technology, and just replacing the steppers in one of the lines with the maskless ones.

For the closed cell line, which problems are you seeing? Any special use cases for making chips on a process that emphasizes uniquness so much? I mean, apart from maybe being able to do AOI after the front of line processing to hard-route metal around (presumed) defects, in order to reduce the cleanliness requirements for actual monolithic wafers. I mean like if you have a 2D, routing mesh of compute, and you need to worry about routers having defects that tank your yield in wafer-scale chips, you can design the front of line masks to allow wiring one or maybe even more clock delays into the mesh link (without significant cost to the attainable frequency/minimum delay) and also just not connect the link from one or more neighbors over (on the other side of the defect router) to the defect circuity, so that routing between the nodes around the defect one isn't impacted, and neither are any delay cycles. The one node is broken, but it'd just be something a compiler would have to work around.

Other things like hardwired crypto keys might be of use, or hardwired logic for these <15 ppi very, very wide aspect ratio LED screens that are anyway configured for some fixed text to scroll by. Or some analogue IC that is detuned from theoretical values to compensate for the not-precisely-manufacturable discrete capacitors (and inductors), as e.g. the needed Q-factor/voltage of the resonance doesn't allow mechanical trimming components to be used, as they'd induce corona discharge if close enough to not murder the Q-factor.

Digital control is in nowadays even for fast feedback loops, but you can't beat the latency of analogue PD controllers. Good luck compensating single-digit MHz vibration actively with a piezo and e.g. optical interference pattern contrast sensing with some photodiodes like done with 4 of the latter for a CD drive. I'm confident that the power driver is a harder part, given that you want it to follow lumped-element behavior and not distributed-element effects, so you can cope with random noise of sufficiently low frequency to fall within the bandpass range of the control circuity.