ARM Assembly Is Too High Level: ROR and RRX

Re:ARM Assembly Is Too High Level: ROR and RRX by kccqzy on Wednesday September 26, 2018 @05:39AM (#18074292)

I don't think this characterizes an instruction set as CISC at all. In any case, having those "special cases" means that if an operation can be subsumed by another operation, the former is just an alias of the latter on the instruction encoding level, thereby reducing the actual number of instructions. Think of it as syntactic sugar.

I still find this classic to be the best explanation of the technical characteristics of CISC/RISC: https://userpages.umbc.edu/~vijay/mashey.on.risc.html

Here's a short summary:

Most RISCs:

- Have 1 size of instruction in an instruction stream

- And that size is 4 bytes

- Have a handful (1-4) addressing modes

- Have NO indirect addressing in any form (i.e., where you need one memory access to get the address of another operand in memory)

- Have NO operations that combine load/store with arithmetic, i.e., like add from memory, or add to memory.

- Have no more than 1 memory-addressed operand per instruction

- Do NOT support arbitrary alignment of data for loads/stores

- Use an MMU for a data address no more than once per instruction

- Have >= 5 bits per integer register specifier

- Have >= 4 bits per FP register specifier

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Re:ARM Assembly Is Too High Level: ROR and RRX by simias on Monday October 08, 2018 @03:24AM (#18164901)

IMO RISC is more a philosophy than a technical term, your definition is something that was created post-facto to try and come with a definition. It's more like "all currently accepted RISC IAs have the following characteristics" but I disagree that they're an appropriate definition. For instance:

>Have 1 size of instruction in an instruction stream and that size if 4 bytes

So that means that Thumb isn't RISC because it has 16 bits instructions and a few double-width opcodes? Even though its instruction set if effectively even more restricted than ARM? That doesn't make sense to me.

>Do NOT support arbitrary alignment of data for loads/stores

MIPS has SWL/SWR LWL/LWR, does that count? I suppose you could say that RISC has no support for arbitrary alignment in regular load and store instructions but again, is that really enough to disqualify an IA? What if I made a tweaked MIPS CPU with an identical instruction set with the only difference being that unaligned LW/SW would work as intended instead of raising an exception, would it stop being RISC?

>Have >= 5 bits per integer register specifier, Have >= 4 bits per FP register specifier

That actually disqualifies ARM32 as far as I can tell, since it only has 16GPRs encoded using 4 bits. I fail to see how this small encoding detail is relevant to RISC anyway. Maybe it just meas that you need at least 32GPRs?

Wikipedia has a much broader (and IMO more reasonable) definition of RISC:

>Various suggestions have been made regarding a precise definition of RISC, but the general concept is that such a computer has a small set of simple and general instructions, rather than a large set of complex and specialized instructions.

By this definition an instruction such as "Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero" is very much un-risc-y.

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Re:ARM Assembly Is Too High Level: ROR and RRX by Symmetry on Wednesday September 26, 2018 @08:26AM (#18075183)

Yes, but by that classic definition ARM is certainly one of the CISCiest of the RISC architectures with its condition codes, barrel shifter, auto-increment loads and stores, and load/store multiple. And x86 is one of the RISCiest of the CISCs with its lack of indirect memory access. All of which might represent a sort of semantic happy medium.

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