There are a few instructions that nearly every modern processor ended up adopting, but RISC-V still lacks. Off the top of my head, (with the RV ISA developers response in parenthesis):

- bitwise rotate (let them eat macro-op fusion)

- byte and bit swapping (strictly missing from RV, although proposals exist)

- leading zero count, trailing zero count, and popcount (strictly missing from RV, proposals exist)

- efficient multiword arithmetic (let them eat macro-op fusion, or long dependency chains)

- base + [scaled] index addressing modes (you don't really need those)

- multi-register save/restore instructions (ARMv8 doesn't have them / RVC is equivalent in density to ARMv8, nanoMIPS is irrelevant, let them eat millicode)

So yeah, there are deficiencies. None of them are crippling, but I wouldn't say that RV is super-wham-o-dyne, either.