I did mention that async design was hard and bug prone, and that was not my point at all.

My point was that clocked design is such an orthodoxy that you can almost not find any information and more specifically methodologies to attack asynchronous H/W design problems.

To use an analogy, the vast majority of electronics is digital these days, because analog is darn hard and digital brings in discipline and guarantees but it doesn't mean the subject of analog electronics isn't explored just because it's hard.

It's not an orthodoxy, you just can't do anything real in a reasonable timeframe for reasonable manpower that a sync CMOS design can't do better (in general). So there's nobody to discover all the secrets of async methodology.

That is, outside of things like SERDES links, which are a tiny dark cabal that holds their secrets close :)

Indeed, analog circuits are well researched topic. However, I think it's important to understand that the transistor CPU is a fairly new topic. In fact, the whole of computer science is a relatively new topic.

As for research there's plenty. I linked slides from an undergraduate course because you wrote that your background leaned more towards computer science. Finding research in this topic is as easy as doing a search through IEEE.

http://asyncsymposium.org/async/Welcome.html http://www.async.caltech.edu/publications.html

Analog electronics is basically only used nowadays when digital literally cannot accomplish the task (RF, SERDES, ADC/DAC). I haven't seen any asynchronous designs that can do things sync designs can't do, just that claim to be better by some metric. Until now, process improvements have made these benefits of async design not worth the additional design effort.

I agree that async design is worth researching, but there is a good reason that undergrad level digital design assumes sync.

The game may change going forward since Dennard scaling is dead. 'deepnotderp probably has some interesting insights on this topic, perhaps he will chime in.