They have been some attempt. E.g: the mit project called sirus that used python 2.5 as a dsl to describe high level components you could combine and reuse and then process to generate system c or verilog.

Unfortunaly, while the tool is pretty nice, it never resulted in major adoption (qualcom has some tool using it internally and a few others) and we haven't seen the idea of making reusable libs and components florish.

Somebody would need to find this project and up it to python 3.6. With current tooling, it would make writting code in it really nice and ease the creation of reusable components.

Reusability in raw verilig is hard