I don't buy it. Having Cadence and Synopsys involved it is like DARPA invites Mathworks to do an open-source version of Matlab.

I don't believe keeping barrier of entry high in an industry is a good thing for companies in that industry.

Quite the contrary, lowering barriers creates more opportunities and thereby new scope for growth.

It took MSFT 30 years to finally understand that lesson and start offering a free suite of dev tools.

The EDA industry still hasn't groked that lesson.

Microsoft knew what they were doing: using secrecy, obfuscated formats/protocols, copyright law, and patent law to block as much competition as possible. They made billions in the process. The EDA vendors do something similar but mostly acquire competitors. There's just three of them covering the basics parts of ASIC design. They aren't competing on driving prices down, either.

So, their strategy is smart until they, like Microsoft, get in a situation where less and less customers need them. I did think one could do a more open version of EDA, though. I was gonna try to talk to someone at smaller player, Mentor, but they got bought. Im keeping my eyes open for new players wanting a differentiator.

The participating companies makes chips that requires a huge amount of resources to make them happen: design engineering time, CAD software, tape-out cost, validation engineering time, ...

The CAD software is expensive, but it's not barrier of entry expensive compared to design engineering time, tape-out cost etc.

If the CAD software cost gets reduced, it would result in a cost reduction of all companies involved while still having a barrier of entries that's be way too high for anyone but the best funded companies.

From the article: "If successful, the programs “will change the economics of the industry,” enabling companies to design in relatively low-volume chips that would be prohibitive today. "

Yes. But it won’t change a thing for the big companies: they don’t make those low-volume (and low effort!) chips.