Well, consider that MCMs have existed for decades: https://en.wikipedia.org/wiki/Multi-chip_module

So in many regards, these "chiplets" aren't new, at least conceptually. What needs to happen is for the protocols to be redefined and respec'd for today's technology.

In particular: the silicon interposer allows for many more connections than previous technologies, as well as much lower power consumption. So protocols need to be designed with those power-requirements and huge "pin counts" so to speak.

Consider HBM2: its a 1024-bit bus. But there's four of them per Vega64, so that's 4096-wires on the interposer connecting the GPU to the RAM.

This is a level of integration never before seen, even in the MCM world. The future is with larger pin counts at far lower energy costs than before.

So its not so much that these problems are purely research. They're closer to engineering. There already exist protocols for cache coherency or fast communications at these levels, they just need to be tweaked for the new scale of things.

There's already been an example of this with the AMD + Intel combination sold by Intel in the Hades Canyon NUC. It's an Intel CPU and an AMD GPU in a single package on some sort of interposer.

The more common approach is via SOCs though.