Re:AMD Tackles Coming “Chiplet” Revolution With New Chip Net...
by dragontamer on Sunday June 24, 2018 @11:49AM
(#17386965)
Not quite.
Intel's EMIB is a specific design that is cheaper than a full silicon interposer.
As such, EMIB is a methodology which may enable chiplet designs in the future. Well, I guess Intel did marry that Xeon+FPGA chip earlier this year, so EMIB is deployed today. That's probably as "chiplet" as you can get, since the FPGA is actually on the CPU's cache-coherence network.
Alas: Intel's UPI (ultrapath interconnect) is designed for PCB boards. Its how 2socket or 8-socket chips communicate together. So its not really doing anything "special" with EMIB, its just shrinking down a PCB in some respects.
> My guess is that future APU will be chiplet based design as well.
It really depends on what the "sweetspot" is. Below a certain size, you don't get any yield benefits. While above a certain size, it becomes expensive... and then impractical... to build chips.
AMD's APUs are generally seen as low-cost cheap chips. At under 200mm^2, its likely that APUs will simply be more efficiently manufactured as single pieces of silicon.
Now, if AMD decided to make a "high end" APU, kinda like their Intel+AMD collaboration project Hades Canyon, then maybe that would use chiplets of some kind. From my understanding, the Hades Canyon collaboration project is just running PCIe however, so its not really a chiplet yet.
Intel's EMIB is a specific design that is cheaper than a full silicon interposer.
As such, EMIB is a methodology which may enable chiplet designs in the future. Well, I guess Intel did marry that Xeon+FPGA chip earlier this year, so EMIB is deployed today. That's probably as "chiplet" as you can get, since the FPGA is actually on the CPU's cache-coherence network.
Alas: Intel's UPI (ultrapath interconnect) is designed for PCB boards. Its how 2socket or 8-socket chips communicate together. So its not really doing anything "special" with EMIB, its just shrinking down a PCB in some respects.
> My guess is that future APU will be chiplet based design as well.
It really depends on what the "sweetspot" is. Below a certain size, you don't get any yield benefits. While above a certain size, it becomes expensive... and then impractical... to build chips.
AMD's APUs are generally seen as low-cost cheap chips. At under 200mm^2, its likely that APUs will simply be more efficiently manufactured as single pieces of silicon.
Now, if AMD decided to make a "high end" APU, kinda like their Intel+AMD collaboration project Hades Canyon, then maybe that would use chiplets of some kind. From my understanding, the Hades Canyon collaboration project is just running PCIe however, so its not really a chiplet yet.