Re:Intel's 10nm Is Broken, Delayed Until 2019
by Nokinside on Friday April 27, 2018 @10:31AM
(#16941003)
Numbers I mentioned are just physical maxims.
In reality its the signal speed relative to jitter, time interval errors and data setup times that complicate the design and signal integrity.
If the clock is 3GHz, the margin of error is the fraction of the time of the clock rate. You need to divide the chip into clock regions and add local cache for each core because fetching data far away is too slow.
In reality its the signal speed relative to jitter, time interval errors and data setup times that complicate the design and signal integrity.
If the clock is 3GHz, the margin of error is the fraction of the time of the clock rate. You need to divide the chip into clock regions and add local cache for each core because fetching data far away is too slow.