Volatile is ok, as long as it honors barrier commands.

I think the bigger issues are bandwidth and power consumption. If software is doing heavy IO, it doesn’t really want to have to contend with the HMB for PCIe and memory bandwidth.

Also, a DRAM chip is a DRAM chip. I’d rather pay a couple dollars for a local DRAM chip in the NVMe device than a couple dollars for extra host RAM that will be permanently reserved for the HMB.

The heavy IO case is addressed by write-back characteristic of block devices. In the end, the cache is in host RAM regardless of the underlying device type.

I think you may be misunderstanding the issue. A flash controller that tries to look like a block device needs to manage a mapping between logical and physical blocks along with various other pieces of metadata. The on-flash representation needs to be structured in a flash-friendly way, which often means that it’s not efficient to find the metadata needed to process an IO request unless that metadata is cached in memory.

On an HMB device, the metadata will be cached in host memory, which will likely adversely affect performance and power efficiency.