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A comment on Why Does “=” Mean Assignment?.

Re:Why Does “=” Mean Assignment? by slededit on Tuesday April 10, 2018 @03:33PM (#16804436)
The '=' sign is used because after that statement the variable will indeed have equality with the r-value.

Coincidentally in async languages like Verilog there is a another assignment operator '<=' which means that the variable won't take the new value until the next clock cycle (or more explicitly the next evaluation of the process block). '=' exists also and has the same meaning as with traditional languages.

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Re:Why Does “=” Mean Assignment? by paulddraper on Tuesday April 10, 2018 @04:40PM (#16805108)
By that logic,

    a <= 1
Should set a to the minimum of a and 1. I.e. after that statement the variable will indeed be less than or equal to the RHS.
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Re:Why Does “=” Mean Assignment? by slededit on Tuesday April 10, 2018 @04:41PM (#16805133)
Languages borrowing the syntax don't need to follow its logical consistency. I just thought it was an interesting anecdote.
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Re:Why Does “=” Mean Assignment? by lionel- on Wednesday April 11, 2018 @02:14AM (#16808493)
What about `a = a + 1`?
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Re:Why Does “=” Mean Assignment? by slededit on Wednesday April 11, 2018 @02:15PM (#16813845)
The r-value is ephemeral it doesn't exist once the statement ends.
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