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A comment on Apple Plans to Use Its Own Chips in Macs from 2020, Replacing Intel. Parent comment

Re:Apple Plans to Use Its Own Chips in Macs from 2020, Repla... by throwaway2048 on Monday April 02, 2018 @05:34PM (#16739595)
emulating x86 on ARM with any kind of real preformanceis additionally tricky because the x86 archetechure has very strong memory gaurentees (dosent matter if memory is aligned, dosent matter when in the instruction pipeline you access it, etc) that ARM isnt even close to matching.

Emulating that requires a massive performance hit, because you essentially have to check every single memory access to make sure its not doing something invalid on ARM.

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Re:Apple Plans to Use Its Own Chips in Macs from 2020, Repla... by zlynx on Monday April 02, 2018 @08:15PM (#16740714)
From what I've heard, x86 to PPC or ARM emulators are doing dynamic recompiling and instrumentation. It catches the illegal memory accesses and rebuilds the code responsible to add paths with slower code with alignment compensation.

A lot of x86 code is aligned for speed already so it's a pretty safe bet to assume alignment and fix it up if wrong.

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Re:Apple Plans to Use Its Own Chips in Macs from 2020, Repla... by Someone on Monday April 02, 2018 @06:42PM (#16740142)
…or you design your own ARM CPU that handles unaligned memory accesses fine, and run your emulator on that hardware.
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Re:Apple Plans to Use Its Own Chips in Macs from 2020, Repla... by readittwice on Tuesday April 03, 2018 @09:29AM (#16744398)
AFAIK the ARM license doesn't allow to invent arbitrary extensions to the ISA. So this might not be allowed.
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Re:Apple Plans to Use Its Own Chips in Macs from 2020, Repla... by Someone on Tuesday April 03, 2018 @12:34PM (#16746369)
Apple has an architectural license. I would expect that allows them to add instructions (assuming modern ARM still has the concept of instruction set extensions)

Google didn’t answer that for me, but I found out that there now is a ”cp15 sctlr[1] (alignment bit)”. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.... says this about it:

”3.5.1. Alignment faults

If alignment fault checking is enabled (the A bit in CP15 c1 is set), the MMU generates an alignment fault on any data word access if the address is not word-aligned, or on any halfword access if the address is not halfword-aligned, irrespective of whether the MMU is enabled or not. An alignment fault is not generated on any instruction fetch or any byte access.”

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