From my understanding, many FPGAs do not have a dedicated reset distribution network. Instead, P&R consumes a ton of resources to propagate resets across the chip.
My information could be out of date though!
My information could be out of date though!
It makes no difference for most FPGAs. Most have dedicated resources dedicated to resets and consume equal resources for async and sync resets.
For ASIC, sync resets these days are considered safer against glitches because they only have an impact during a rising edge of the clock instead of all the time.
But it's not something to be super religious about.