Re:45 year CPU evolution – one law and two equations
by slededit on Monday March 05, 2018 @02:22PM
(#16523601)
The bottleneck for DDR memory isn't really the memory controller but rather the memory bus itself. Moving the controller won't change that.
Its very rare to get anywhere close to 100% bus utilization. HMC's real advance is switching to independent serial links which we know how to scale better than parallel busses. Its this improved bandwidth that allows you to pack in more parallelism. We could have more banks in traditional DDR memory but there isn't much point because the data bus couldn't feed it.
Indeed. So there's some parallelism that can be captured, but they're managed by the CPU instead of the Memory.
Because HMC abstracts away the protocol into a packet-based innately out-of-order protocol, and because the "memory controller logic" has been moved to an area physically as-close-as-possible to the RAM itself, it can achieve much higher degrees of parallelism.
Case in point: a single stack of HMC has 128 banks of parallelism across 4-vaults (I would argue that a "vault" is roughly equivalent to a DDR4 channel): https://www.micron.com/parts/hybrid-memory-cube/hmc-sr/mt43a...