To prevent glitches it rarely problem but sometimes happens: imagine that default pin state must be high (on reset pin are floating) and moment you set pin mode to output it goes low, because data register is 0

Consider a I/O pin set to open-drain drive. It either actively pulls the output pin to the ground rail, or the I/O floats. Externally, you have a pull-up resistor.

If there are multiple chips connected in open-drain, you write the I/O pin to 0 or 1 to either ground or float the pin. You read the I/O pin to see if anyone else has grounded it if you haven't. This was called "wired-OR" in the old days. (It's really AND, but was commonly used in DeMorgan equivalent form for communication buses before tri-state drivers became a thing. I'll get my cane and hobble back to my rocking chair now..)

I think in the old days, before CMOS, this was called open-collector. I had learned about it in first semester digital logic not too long ago playing with the "high speed" 7400 series. If I remember correctly, the latch needs to support the open collector capability, but the reason escapes me.

Open collector if you have a bipolar technology. Modern microcontrollers are CMOS, so the pull-down transistor has a drain, not a collector. TTL is bipolar, so the transistor has a collector.

As mentioned above, in some uC's the output register defines the pull direction when the pin is an input.

In other cases, you want to avoid glitching when the pin switches to an output on startup.

It can be used to implement capacitive touch.