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Re:I.MX7 M4 Atomic Cache Bug by cesarb on Monday February 19, 2018 @06:16AM (#16412196)
> and never really dug into x86 so I'm not very familiar with the corresponding instructions there.

The x86 has no corresponding instructions (other than perhaps the very recent and not yet popular transactional extensions). Instead, the x86 world uses an "atomic compare and exchange" instruction. Wikipedia articles: https://en.wikipedia.org/wiki/Compare-and-swap versus https://en.wikipedia.org/wiki/Load-link/store-conditional

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