FPGAs start from far, far behind on the performance end though (by a factor of several dozen). FPGA vendors compete to shift as much as they can out of configurable logic and into lithographically-defined IP blocks because of this severe disadvantage. A modern FPGA will be strewn with hardwired serial interfaces, memory controllers, CPU cores, and the like. Taking advantage of these is almost always a gigantic performance win, and that's assuming the functionality they provide is even possible in configurable logic (e.g. try implementing a 32Gbps serial port using only configurable 500MHz logic).

FPGAs don't trend towards openness and you have to get a 100x win from their flexibility to break even on performance.