Re:Reverse-engineering FPGAs [video]
by gruez on Friday January 19, 2018 @09:35AM
(#16186452)
How does that even make sense? It's like saying intel cripples their processors so they can sell more.
[ Parent
| on HN ]
No, it's like saying the only compiler for x86 is created by Intel (paid for by the sale of processors) and they therefore don't have an incentive to make the compiler particularly good at optimizing. If it does a better job at optimizing, people can get away with cheaper processors.
I'm not saying there is any intentional area bloating going on, just that there is little incentive to make Vivado better at optimizing.
Read https://www.bunniestudios.com/blog/?p=5018 to see where I'm coming from.
EDIT: It makes a lot of sense in my head, but perhaps I'm overlooking something important. I'd be interested to read in more detail why it doesn't make sense to you.
Quite a few groups of lower-end Xilinx FPGAs (e.g, XC7S6/15, or XC7A15T/35T/50T) are all physically the same silicon, but are sold under multiple SKUs with different chip IDs, with the synthesis software forced to leave some percentage of the area unused. Open-source synthesis tools would probably break this part of their business model. :)