Meltdown Proof-of-Concept

Re:Meltdown Proof-of-Concept by spullara on Tuesday January 09, 2018 @04:04PM (#16110044)

i'm not so sure. memory accesses are so slow (hundreds of cycles) it probably wouldn't be that much slower to issue them a few instructions later. when it was introduced memory access and cycles were much closer together, only a few cycles and it saved a huge amount of time.

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Re:Meltdown Proof-of-Concept by gpderetta on Tuesday January 09, 2018 @05:28PM (#16110751)

Main memory access take an order of hundred cycles. D1 cache hit access usually take usually 3-4 cycles. Microarchitecture designers will take heroic efforts to even shave a single cycle here. Adding an overhead of even a couple of cycles would be a huge deal.

Having said that, AMD CPUs are the existence proof that you can be immune to meltdown with no significant overhead.

Spectre is a completely different issue though.

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Re:Meltdown Proof-of-Concept by londons_explore on Tuesday January 09, 2018 @06:08PM (#16111027)

AMD CPUs have pretty poor single threaded performance.

Perhaps that because they haven't taken the speed short-cuts that Intel took...?

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Re:Meltdown Proof-of-Concept by jandrese on Tuesday January 09, 2018 @11:28PM (#16112565)

Didn't Ryzen close the single thread performance gap quite a bit?

But yeah, protecting against it means implementing memory protection in more places in the CPU. More gates and the possibility of becoming a bottleneck.

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Re:Meltdown Proof-of-Concept by arcticbull on Wednesday January 10, 2018 @04:15AM (#16113530)

With Ryzen, they're pretty much equal on an IPC basis.

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