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A comment on Building a More Secure World with the RISC-V ISA. Parent comment

Re:Building a More Secure World with the RISC-V ISA by jabl on Sunday January 07, 2018 @01:49PM (#16092003)
> >can actually combine x86 ISA instruction pairs into a micro-op

> More complexity, and more tickets for the implementation bug lottery.

Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.

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Re:Building a More Secure World with the RISC-V ISA by snvzz on Sunday January 07, 2018 @02:54PM (#16092327)
It does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence.

Very nice and very clean when done as they propose with this RISC ISA.

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