Re:Building a More Secure World with the RISC-V ISA
by jabl on Sunday January 07, 2018 @01:49PM
(#16092003)
> >can actually combine x86 ISA instruction pairs into a micro-op
> More complexity, and more tickets for the implementation bug lottery.
Well, the slides (and accompanying paper) you linked to earlier in this thread makes the cases for using macro-op fusion in high-performance RISC-V designs.
Re:Building a More Secure World with the RISC-V ISA
by snvzz on Sunday January 07, 2018 @02:54PM
(#16092327)
It does and I'm well aware of it. It proposes settling on an idiom rather than a new instruction, for a very common sequence.
Very nice and very clean when done as they propose with this RISC ISA.
In RISC-V parlance, it'd be the new vector extensions. They're pretty cool as they've made the width variable. Refer to 7th workshop proceedings.
>micro-ops
Are a fancy word. It just means a (hidden) RISC architecture. There's a bunch of RISC architectures out there, but they get down to doing more or less the same things.
Most RISC and CISC architectures in use today are evolved from ones existing back in the 80s, and carry a lot of baggage. RISC-V benefits from having a clean slate at this, using the experience of existing ISAs.
>can actually combine x86 ISA instruction pairs into a micro-op
More complexity, and more tickets for the implementation bug lottery.