Building a More Secure World with the RISC-V ISA

Re:Building a More Secure World with the RISC-V ISA by fulafel on Sunday January 07, 2018 @09:03AM (#16090881)

a pipeline flush and unprefetched instruction fetch on each branch (20-25% of insns) would dramatically slow down the CPU. With branch prediction you can potentially have correctly predicted branches take zero cycles, even without speculative execution.

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Re:Building a More Secure World with the RISC-V ISA by blattimwind on Sunday January 07, 2018 @03:03PM (#16092367)

Using a branch predictor to start execution of a branch is speculative execution.

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Re:Building a More Secure World with the RISC-V ISA by fulafel on Sunday January 07, 2018 @03:38PM (#16092558)

In established computer architecture terminology, speculative execution is reserved for speculating past branches. (Speculation meaning something that may not pan out...)

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