Re:Building a More Secure World with the RISC-V ISA
by jabl on Sunday January 07, 2018 @04:46AM
(#16090114)
Rocket has a branch predictor; if you're not going to do any kind of speculation, why have it in the first place?
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Re:Building a More Secure World with the RISC-V ISA
by fulafel on Sunday January 07, 2018 @09:03AM
(#16090881)
a pipeline flush and unprefetched instruction fetch on each branch (20-25% of insns) would dramatically slow down the CPU. With branch prediction you can potentially have correctly predicted branches take zero cycles, even without speculative execution.
Re:Building a More Secure World with the RISC-V ISA
by blattimwind on Sunday January 07, 2018 @03:03PM
(#16092367)
Using a branch predictor to start execution of a branch is speculative execution.
Re:Building a More Secure World with the RISC-V ISA
by fulafel on Sunday January 07, 2018 @03:38PM
(#16092558)
In established computer architecture terminology, speculative execution is reserved for speculating past branches. (Speculation meaning something that may not pan out...)
Re:Building a More Secure World with the RISC-V ISA
by tscs37 on Sunday January 07, 2018 @05:23AM
(#16090236)
Preloading instructions into the cache or only executing instructions speculatively which only modify the CPU's internal state and no caches.
Re:Building a More Secure World with the RISC-V ISA
by rayiner on Sunday January 07, 2018 @11:31AM
(#16091375)
This shouldn’t be downvoted. The reason to have a branch predictor is so you can speculatively execute down the predicted path when you hit a branch. Although I think the Spectre attack requires not only speculation, but the ability to perform loads out of program order.
Re:Building a More Secure World with the RISC-V ISA
by fulafel on Sunday January 07, 2018 @03:48PM
(#16092610)
It's a reason, but not the only reason. In-order superscalar processors rely heavily on branch prediction too.
Re:Building a More Secure World with the RISC-V ISA
by al2o3cr on Sunday January 07, 2018 @03:42PM
(#16092578)
The direction of a branch isn't going to be known until a couple stages into the pipeline ("EX" in the classic RISC version). Ideally, the preceding stages in the pipeline will be fed correctly - that can either be the instructions immediately following the branch (as in the "branch delay slot(s)" found in some architectures) or the instructions at where the CPU thinks the branch will lead.
Re:Building a More Secure World with the RISC-V ISA
by NinjaKitten on Sunday January 07, 2018 @05:21AM
(#16090227)
AFAIK its load store unit does plenty speculation.