Re:Intel Gears Up for FPGA Push
by ngsayjoe on Tuesday October 03, 2017 @01:16PM
(#15394059)
You can always use third-party EDA tools if you have the money rather than the vendor bundled free software. Eg Cadence, Mentor Graphics, etc.
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Don't you need the vendor-specific backend for the physical P&R?
Yes, you do need the vendor's place-and-route. PAR performance is as good as you could expect though.
Most complaints about vendor software are closer to the front of the flow. Examples...
* Poor language support (applies for both SystemVerilog and VHDL)
* Not enough transparency and access to primitives and IP blocks, resulting in poor ability to automate
* Generally buggy elaboration and synthesis results, sometimes even causing the tool to crash
My opinion is that the FPGA companies spend too much money improving the HLS (c-to-gates) and IP wizard experience, in an attempt to make their devices more accessible to the mythical software engineer who wants to use an FPGA.
They should have spent that time and money supporting language standards, and improving the RTL experience, which is how most engineers use their products.