LoweD

Yes, you do need the vendor's place-and-route. PAR performance is as good as you could expect though.

Most complaints about vendor software are closer to the front of the flow. Examples...

* Poor language support (applies for both SystemVerilog and VHDL)

* Not enough transparency and access to primitives and IP blocks, resulting in poor ability to automate

* Generally buggy elaboration and synthesis results, sometimes even causing the tool to crash

My opinion is that the FPGA companies spend too much money improving the HLS (c-to-gates) and IP wizard experience, in an attempt to make their devices more accessible to the mythical software engineer who wants to use an FPGA.

They should have spent that time and money supporting language standards, and improving the RTL experience, which is how most engineers use their products.

Last time I checked out Christiaan Baaji's CLASH, it was a Haskell DSL for generating RTL. That is neat, but it doesn't involve any LLVM-like abstraction of FPGA primitives for synthesis.

That would be more than neat, revolutionary really. But it would require buy-in from the major vendors, in the form of publishing many low-level device details.