BOOM v2: an open-source out-of-order RISC-V core

Re:BOOM v2: an open-source out-of-order RISC-V core by PhilWright on Tuesday September 26, 2017 @07:06PM (#15343420)

Yes, I am about 2/3rds of the way through designing and building a single cycle, modified Harvard architecture, RV32E CPU. You can check it out here...

https://hackaday.io/project/18491-worlds-first-32-bit-homebr...

Although a projected speed of 1Mhz and the size might exclude it from your own project!

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Re:BOOM v2: an open-source out-of-order RISC-V core by gok on Tuesday September 26, 2017 @07:10PM (#15343447)

I meant more like... just using straight Verilog, but very impressive!

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Re:BOOM v2: an open-source out-of-order RISC-V core by dnautics on Tuesday September 26, 2017 @07:13PM (#15343465)

I'm not sure I would recommend using straight verilog for something of that magnitude. I do know that some folks that used Perl to assemble verilog into a computer chip, but they regretted the engineering debt that came with it (and the hire they made that instituted that decision).

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Re:BOOM v2: an open-source out-of-order RISC-V core by senatorobama on Tuesday September 26, 2017 @07:15PM (#15343470)

> Perl to assemble verilog into a computer chip

This is absurdly common.

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